Scaling, in image input/output apparatuses such as digital copiers and in image processing apparatuses such as personal computers, has come to be a very important feature. Scaling is frequently used in image input/output apparatuses in particular, which are usually equipped with a special scaling circuit.
The operations of a conventional scaling circuit are shown schematically in FIG. 34, in which 3401 denotes the scaling circuit, 3402 denotes an entire scaled input image to be scaled, and 3403 denotes the entire output image after scaling. Reference numeral 3404 denotes the pixels prior to scaling and 3405 denotes the pixels after scaling.
The numbers shown inside the images denote the order in which the pixels of the image are input to or output from the scaling circuit 3401.
FIG. 35 is a block diagram showing the structure in detail of a conventional scaling circuit 3401. In FIG. 35, reference numeral 3501 denotes a line buffer, 3502 denotes a vertical filter, 3503 denotes a shift register and 3504 denotes a horizontal filter. The detailed structure of the horizontal and vertical filters is shown in FIG. 36.
The conventional scaling circuit 3401 shown in FIG. 34 accepts image data (that is, pixel data) of a single page of imagery in the order in which this data is scanned (hereinafter order of scanning), and outputs the scaling results in the order of scanning.
A description is given of the scaling process performed inside the conventional scaling circuit 3401 using FIG. 35.
First, pixel data inputted to the scaling circuit 3401 from an external source is stored in the line buffer 3501. Then, the vertical filter 3502 filters a plurality of image data having the same position in the horizontal direction and being shifted one line each in the vertical direction (eight lines in FIG. 35). After this vertical direction filter processing has been performed, the resulting image data is input to the shift register 3503 for horizontal scaling and image data filter processing (consisting of eight pixels in FIG. 35) is performed in the same manner as vertically.
FIG. 36 shows the operation of a filter processing circuit. In FIG. 36, reference numeral 3601 is a filter coefficient generator circuit, 3602 is a multiplier circuit and 3603 is an adder circuit. A filter coefficient is output from the filter coefficient generator circuit 3601 and image data continuous in either the vertical or horizontal directions is input from either the line buffer 3501 or the shift register 3503. Then, each pixel of the image data is multiplied by the filter coefficient corresponding to that pixel at the multiplier circuit 3602, after which all calculation results are added at the adder circuit 3603 and output.
The foregoing describes the conventional scaling process. However, as disclosed in Japanese Laid-Open Patent Application No. 2002-8002, the Applicant has proposed an image input/output apparatus in which the processing blocks perform image processing in tile image units. The structure of the image processor of such an image input/output apparatus lends itself to integrated circuit (IC) chip formation, and a scaling circuit 3401 can be provided as one of the processing blocks.
However, as the amount of image data to be processed continues to increase at an outstanding rate, the conventional scaling circuit 3401 like that described above would need a very large buffer in order to perform scaling. The circuit shown in FIG. 35, for example, requires an 8-line line buffer, and in the case of an A4-size sheet, a 6,000 dpi image would therefore require a 7,000-pixel buffer.
Moreover, particularly when mounting a scaling circuit on the image input/output apparatus described above, which manages image data in tile image units, the conventional scaling circuit would still require a very large line buffer even if the scaling circuit were mounted in a single chip, and so is not practical when it comes time to package the whole as an IC.
Similarly, although it is possible to configure an apparatus so that no line buffer is provided on an IC chip that includes the scaling circuit and a manageable external chip memory is used instead of the line buffer. However, in such a structure access to the external memory is concentrated and the processing speed of the scaling circuit is limited.